1. Field of the Invention
The present invention relates to electrically programmable and erasable non-volatile memory and integrated circuits including such memory, and more particularly to architectures for such devices supporting byte erase.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies, including flash memory, are being adapted to many applications. Technologies based upon floating gates like standard EEPROM, or charge trapping layers like oxide-nitride-oxide memory cells NROM, are typically programmable and erasable many times. In typical flash memory technologies, the erase processes are executed over an entire array, or large sections of memory cells in an array, in parallel. Thus, in order to erase one target byte, the erase process is executed that erases the array or section, and the portions of the section other than the target byte must be re-programmed, in procedures referred to as erase/re-program cycling. Erase/re-program cycling is relatively time-consuming, particularly when the size of the section being erased is large.
Also, flash memory technologies have limited lifetimes, expressed as a number of times that the memory cell can be erased or programmed before failure. Because erase/re-program cycling requires re-programming of the erased sections even when the data in a majority of the erased memory cells is not being changed, it significantly limits the lifetime of the memory array.
Accordingly, it is desirable to provide systems and methods for erasing flash memory arrays byte by byte.